The present invention is generally related to semiconductor devices and, more particularly, to the design of metal contacts and interconnections for semiconductor integrated circuits which reduce passivation cracking and extrusion-short failure caused by electromigration. The invention also relates to providing various processes for obtaining the designed structure.
Integrated Circuits (IC) typically incorporate and rely on aluminum (Al) based interconnections to carry current to and from active devices (i.e., MOSFETS and Bipolar Transistors). Interconnections of copper (Cu) and gold (Au) have also been used and continue to be used for a limited number of applications. The reliability of these interconnections is generally limited by a phenomenon known as electromigration. Electromigration is the motion of metal atoms in a conductor due to the passage of current. It is basically a diffusion phenomenon in which metal ions and vacancies diffuse in opposite directions with the applied electric field appearing to act as the driving force.
Aluminum-based thin-film metallizations, which are widely used to form conductor patterns and silicate integrated circuits, are especially susceptible to failure caused by electromigration. Electromigration can lead to failure in these devices primarily by one of two failure mechanisms. In both mechanisms, diffusion of the interconnect metal occurs along grain boundaries to cause a net amount of aluminum to migrate in the direction of the electron flow. In the first failure mechanism, aluminum diffuses away from a region in the interconnect faster than the availability of additional atoms can take its place. This forms vacancies. The diffusion of aluminum typically occurs from certain regions, often points where three grains touch, to create vacancies which coalesce at points of flux divergence. As a result, voids are left behind at the negative end of the interconnection. With continued aluminum mass transport, the void grows until a failure occurs, in the interconnection, known as a void-open failure. Although a resistance increase is usually observed in multi-layered metallizations before catastrophic failure occurs, single-layered metallizations may show little or no resistance increase before failing catastrophically.
The second mechanism, by which electromigration failure occurs, is caused by the electromigration of metal atoms into a region faster than the atoms escape the region which creates a local pile-up of metal atoms downstream of the electron flow to form hillocks at the positive end of the interconnection. In confined metal interconnects, such as those deposited on an oxidized silicon substrate and covered by a dielectric passivation layer, the accumulation of metal atoms due to continued mass transport exerts pressure on surrounding insulator layers which are contiguous to the interconnect. As the pressure increases due to continued mass transport, cracks form in the insulator into which aluminum can extrude. Short circuit failures, known as extrusion-short failures, occur when the extruded material extends and contacts adjacent interconnection lines to cause electrical short circuits. As microelectronics circuits are made more dense in order to improve performance, the electric fields (and resulting current densities) in the aluminum interconnects increase. Hence, as circuit densities increase, the rate of electromigration also increases.
The points of flux divergence at which void-open electromigration failures are known to occur (and from which, in single-layer metallization structures, corresponding extrusion-short failures result) vary according to the microstructure and morphology of the wiring structure. In thin-film conductors, flux divergences may be caused by non-uniform structures (e.g., discontinuities such as grain boundaries, variation in grain size, and variation in grain orientation) and non-uniform operating temperatures. Prior art efforts at reducing the probability of electromigration failures for a given time, temperature, and current typically include fabricating conducting interconnects which attempt to reduce flux divergence by eliminating structural non-uniformities.
For wiring structures having single-layer metallization interconnections, flux divergences in the metallization conductors commonly occur at discontinuities of grain structures. U.S. Pat. No. 4,438,450 issued to Sheng et al., U.S. Pat. No. 5,101,261 issued to Maeda, and U.S. Pat. No. 5,382,831 issued to Atakov et al., all attempt to reduce the diffusion flux in single-layer metallization interconnection structures by creating a plurality of narrow interconnect conductors for an integrated circuit in place of a single, wider conductor. The plurality of narrow interconnect conductors are provided in widths comparable to the grain size of the metal interconnect to produce a morphology commonly referred to as a xe2x80x9cbamboo microstructure.xe2x80x9d In this manner, the metal grains which extend from top to bottom of the conductor and from one side to the other side of the conductor act as blocking grains to prevent the formation of a continuous path of grain boundaries along the length of the patterned conductor.
As a result, the mass transport of the interconnect metal atoms is retarded which in turn slows the formation of voids and minimizes the associated resistance increase. In turn, because the mass transport of interconnect metal atoms is retarded, the incidence of extrusion-short failures is also reduced by blocking grains in single-layer metallization interconnects because the source of atoms which flow downstream of the current flow is reduced. Thus, by replacing a wide-line interconnect (i.e., an interconnect having widths greater than 1 to 1.5 times the mean grain size) with narrow-line interconnects (i.e., interconnects having widths less than 1 to 1.5 times the mean grain size), the atomic flux due to electromigration along the line is reduced. From this replacement it follows that the integrated circuits containing single-layer metallization interconnects are less likely to fail from electromigration, both from void-open and extrusion-short failures, during operation.
Progress toward device scaling of integrated circuits, however, requires increasing the numbers of wiring levels, defined with greater precision, density, and yield. As noted by Hu et al, xe2x80x9cElectromigration in Al(Cu) two-level structures: Effect of Cu and kinetics of damage formation,xe2x80x9d J. Appl. Phys. 74 (2), pp. 969-978 (1993), the problem of electromigration increases for multi-level interconnect structures because narrower line widths lead to higher current densities. In devices having multi-level wiring levels, however, additional flux divergences may also occur at interfaces between the conductor lines caused by structural non-uniformities such as diffusion barriers between the metallization interconnect layers. Diffusion barriers are particularly are a problem in multi-level structures such as Very Large Scale Integration (VLSI) or Ultra Large Scale Integration (ULSI) devices in which the metallization layers are typically connected by tungsten interlevel connection studs. Because the interlevel connection studs hinder diffusion between various wiring levels, replenishment of depleted metal atoms is prevented, eliminating what is known as the xe2x80x9creservoir effect.xe2x80x9d As a result, voids form upstream of the electron flow in the vicinity of the stud which can lead to a void-open failure thereby decreasing the electromigration lifetime of metal interconnections.
In multilevel wiring structures, the current density near the interfaces between conductor lines may increase due to current crowding. U.S. Pat. No. 5,461,260 issued to Varker et al., attempts to reduce the peak localized interconnect current density by creating a plurality of narrow interconnect conductors near the interlevel contact. It should be understood, however, that Varker et al., disclose a structure where current flows through this structure out of the interconnect and then into the interlevel contact. By well established electronic engineering convention electron flow is in the direction opposite to current flow and thus the disclosed structure applies to the cathode or electron current source end of the structure.
For metallization interconnections in multi-level wiring structures having multi-layer metallization interconnections, the resistance increase due to electromigration void formation saturates (i.e., reaches a maximum value) when the stress gradient induced by electromigration balances the electromigration driving force. As reported by Filippi et al, Appl. Phys. Lett. 69, pp. 2350-52 (1996), for a two-level structure having 0.30 um wide metallization interconnections of aluminum-copper (Alxe2x80x94Cu) sandwiched between redundant layers of titanium (Ti) and titanium nitride (TiN) and tungsten interlevel connection studs at both ends, the maximum absolute resistance change follows a jL2 dependence where j is the current density and L is the distance between the interlevel connection studs. The saturation of the resistance increase indicates the suppression of electromigration-induced damage caused by void formation. A corresponding accumulation of aluminum atoms, however, occurs downstream at the anode end of the conductor which, as reported by I. A. Blech, Electromigration in Thin Aluminum Films on Titanium Nitride, J. Appl. Phys. 47, pp. 1203-08 (1976), results in a stress gradient which opposes the electromigration driving force. In the presence of diffusion barriers, this accumulation of aluminum atoms creates a region in the metal which causes an increased compressive stress to be exerted upon any contiguous insulation layers which are typically present. This accumulation of aluminum atoms and the stress caused thereby can lead to cracking of the insulation, and can cause extrusion of the metal in the cracks thus formed, resulting in extrusion-short failures with other interconnection levels.
A method to suppress electromigration-induced damage in multi-level structures was disclosed by Bui et al., in U.S. Pat. No. 5,712,510. Bui et al., disclose the use of openings filled with insulator to create divergences or discontinuities in the metal flux during electromigration and spaced apart along the conducting layer at a sufficiently small distance. This distance corresponds to the minimum backflow potential capacity, which is related to the stress gradient that opposes the electromigration driving force. It should be understood, however, that the invention of Bui et al. is most effective when implemented in the middle of the interconnection. Bui et al. neither claim nor disclose openings greater than or of the same dimension as the width of the conductive layer. In addition, their invention does not apply to metal interconnections with lengths shorter than the length corresponding to the minimum backflow potential capacity for the metal interconnections.
Methods of reducing the effect of void formation on the electrical resistance of interconnect conductors in multi-level metallization structures have been provided by incorporating multiple continuous redundant conductive layers in each interconnection wiring level. U.S. Pat. No. 4,166,279 issued to Gangulee et al. and U.S. Pat. No. 5,071,714 issued to Rodbell et al. illustrate this approach in which redundant under layers, over layers, or both are incorporated on the sides of the interconnect which do not eliminate the formation of void-open failures; rather, they provide an alternative connective electrical path should a void-open occur in the metal interconnect. The redundant layers typically comprise different elements or compounds, one or more of which has a very high melting temperature or very low diffusion coefficient, compared to the major layer which is chosen for its low electrical conductivity. Typically the grain size of the redundant under layer or over layer of a multi-layer conductor is much less than the width of the conducting interconnect. In these redundant layer structures, the grains of the interconnect metal typically do not extend from the top of the conductor to the bottom of the conductor or from one side to the other side of the conductor. When a void forms because atoms migrate along the length of the line, the redundant layer provides an electrically continuous path so that the increase in resistance caused by any voids which form in the conducting interconnect is negligible and the function of the integrated circuit is not reduced.
Because electron flow is shunted around any voids which may form, extrusion-short failures in such multi-layer metallization structures are not prevented. The observed mean time to failure by resistance increase for such structures depends on current density and not on width. This indicates that the most important diffusion path for atoms of aluminum and copper is not along the boundaries between aluminum grains but is instead at the interface between the titanium aluminide and the aluminum containing copper. Thus, even if any blocking grains or bamboo structures are provided in an interconnect with redundant layers, they are short circuited by diffusion along the interface such that extrusion-short failures may still occur. Although multi-level metallization interconnections having redundant metal layers alleviate void-open electromigration failures in multi-level wiring structures, therefore, the accumulation of interconnect metal atoms in these structures still creates extrusion-short failures and passivation layer cracking which ultimately lead to electromigration failure.
Thus, except for circuits sensitive to small resistance changes, the problem of passivation cracking and extrusion-short failures is the predominant mode of electromigration failure which occurs in multi-level structures having multiple interconnection wiring levels. This failure mode of extrusion failures is especially exacerbated in the case where individual wiring levels have multi-layer structures. In these multi-level wiring structures, passivation cracking and extrusion-short failures are especially exacerbated by the presence of diffusion barriers created by tungsten interlevel connections between interconnection levels having multiple metallization layers such as titanium aluminide, aluminum containing copper, and titanium aluminide.
The present invention provides a process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. First, the invention improves the resistance of the metallization interconnections to extrusion-short electromigration failures and prevents the insulating passivation layers from cracking. Second, the invention reduces the effect of void formation. Specifically, the invention provides a process for producing semiconductor devices having multi-level wiring structures with alternating metallization interconnections and insulating passivation layers. By replacing conventional wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, 1) the incidence of passivation cracking and extrusion-short failures is reduced, and 2) the size of the void and the resistance increase at long times is reduced. The process of the present invention is especially suited for use in multi-level wiring structures in which the wiring levels have diffusion barriers between the wiring levels caused by redundant metallization layers, interlevel connections, or both.